1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a liquid crystal display (LCD) device having a shift register with increased lifetime.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device displays images by controlling light transmittance of liquid crystal. For this, the LCD device is provided with an LCD panel including a plurality of pixel regions arranged in a matrix, and a driving circuit for driving the LCD panel.
The LCD panel includes a plurality of gate lines crossing a plurality of data lines to define a plurality of pixel regions. A thin film transistor (TFT) is provided in each pixel region. A plurality of pixel electrodes and a common electrode are formed in the LCD panel to apply an electric field to the respective pixel regions. Each of the pixel electrodes is connected with one of the data lines through a drain terminal and a source terminal of a corresponding TFT functioning as a switching device. The thin film transistor TFT is turned-on by a scan pulse applied to a gate terminal thereof through the gate line, while a data signal from the data line is charged in the pixel region.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying control signals to control the gate and data drivers, and a power supply for supplying driving voltages for the LCD device. The timing controller controls the driving timing of the gate and data drivers, and supplies pixel data signals to the data driver. The power supply generates driving voltages such as a common voltage VCOM, a gate high-voltage signal VGH, and a gate low-voltage signal VGL by raising or reducing an input power.
The gate driver supplies scan pulses to the gate lines in sequence, so as to sequentially drive liquid crystal cells of the LCD panel by one line. The gate driver includes a shift register for sequentially outputting the scan pulses. The data driver supplies a pixel voltage signal to each of the data lines whenever the scan pulse is supplied to any one of the gate lines. Accordingly, the LCD device displays images by controlling the light transmittance with the electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal by each liquid crystal cell.
FIG. 1 illustrates a shift register according to the related art. As shown in FIG. 1, the shift register according to the related art is provided with ‘n’ stages (AST1 to ASTn) which are connected with one another, and one dummy stage ASTn+1. At this time, each of the stages AST1 to ASTn+1 outputs one scan pulse Vout1 to Voutn+1. The first to n-th stages AST1 to ASTn and the dummy stage ASTn+1 respectively output the scan pulses Vout1 to Voutn+1 in sequence. The scan pulses outputted from the first to n-th stages AST1 to ASTn except the dummy stage ASTn+1 are sequentially supplied to the gate lines, thereby scanning the gate lines in sequence.
In this case, a first voltage source VDD, a second voltage source VSS, and two clock pulses among first to fourth clock pulses CLK1 to CLK4 of the sequence phase difference are supplied to all the stages AST1 to ASTn+1. At this time, the first voltage source VDD is a voltage source of a positive polarity, and the second voltage source VSS is a ground voltage.
In the meantime, a start pulse SP as well as the first voltage source VDD, the second voltage source VSS, and the two clock pulses is also supplied to the first stage AST1 which is positioned uppermost.
An operation of the shift register according to the related art will be explained as follows. First, as the start pulse SP from the timing controller (not shown) is applied to the first stage AST1, the first stage AST1 is enabled in response to the start pulse SP. Then, as the first and second clock pulses CLK1 and CLK2 are applied to the enabled first stage AST1, the first stage AST1 outputs the first scan pulse Vout1, and supplies the first scan pulse Vout1 to the first gate line and the second stage AST2. Then, the second stage AST2 is enabled in response to the first scan pulse Vout1.
According as the second and third clock pulses CLK2 and CLK3 from the timing controller are applied to the enabled second stage AST2, the second stage AST2 outputs the second scan pulse Vout2, and supplies the second scan pulse Vout2 to the second gate line, the third stage AST3, and the first stage AST1. Then, the third stage AST3 is enabled in response to the second scan pulse Vout2, and the first stage AST1 is disabled in response to the second scan pulse Vout2, thereby supplying the second voltage source VSS to the first gate line.
As the third and fourth clock pulses CLK3 and CLK4 from the timing controller are applied to the enabled third stage AST3, the third stage AST3 outputs the third scan pulse Vout3, and supplies the third scan pulse Vout3 to the third gate line, the fourth stage AST4, and the second stage AST2. Then, the fourth stage AST4 is enabled in response to the third scan pulse Vout3, and the second stage AST2 is disabled in response to the third scan pulse Vout3, thereby supplying the second voltage source VSS to the second gate line.
In this method, the fourth to n-th stages AST4 to ASTn sequentially output the fourth to n-th scan pulses Voutn, and apply the outputted fourth to n-th scan pulses to the fourth to n-th gate lines in sequence. As a result, the first to n-th gate lines are sequentially scanned by the first to n-th scan pulses Vout1 to Voutn outputted from the first to n-th gate lines.
After the dummy stage ASTn+1 is enabled in response to the n-th scan pulse Voutn outputted from the n-th stage ASTn, the two clock pulses from the timing controller are inputted to the dummy stage ASTn+1. Then, as the n+1th scan pulse Voutn+1 is supplied to the n-th stage ASTn, the n-th stage ASTn is disabled, and the second voltage source VSS is supplied to the n-th gate line. The dummy stage ASTn+1 provides the n+1th scan pulse Voutn+1 to the n-th stage ASTn to output the second voltage source VSS, and doesn't provide the n+1th scan pulse Voutn+1 to the gate line. Accordingly, the total number of stages including the dummy stage ASTn+1 is larger than the number of gate lines.
Generally, each of the first to n-th stages and the dummy stage ASTn+1 includes a node control unit for controlling the charging and discharging state of first and second nodes, and an output unit for outputting the first scan pulse Vout1 or the second voltage source VSS according to the state of the first and second nodes, and supplying the first scan pulse Vout1 or the second voltage source VSS to the gate line of the LCD panel.
At this time, the first and second nodes are alternately discharged and discharged. In detail, when the first node is charged, the second node is discharged. In the meantime, when the second node is charged, the first node is discharged.
When the first node is charged, the scan pulse is outputted from a pull-up switching device of the output unit. When the second node is charged, the second voltage source is outputted from a pull-down switching device of the output unit. In this case, the scan pulse outputted from the pull-up switching device and the second voltage source outputted from the pull-down switching device are supplied to the corresponding gate line. Herein, a gate terminal of the pull-up switching device is connected with the first node, a drain terminal thereof is connected with a clock line for the clock pulse, and a source terminal thereof is connected with the gate line. The clock pulse is periodically supplied to the drain terminal of the pull-up switching device. At this time, the pull-up switching device outputs any one of the clock pulses inputted by each period at a predetermined point. The clock pulse outputted at the predetermined point corresponds to the scan pulse for driving the gate line. The predetermined point corresponds to a point in which the first node is charged. That is, the pull-up switching device outputs the clock pulse inputted at the predetermined point (the point in which the first node is charged) as the scan pulse. According as the first node is maintained as the discharge state until the next frame is started after the output of the scan pulse, the pull-up switching device outputs one scan pulse by each frame. However, since the clock pulse is outputted several times during one frame, the clock pulse is inputted to the drain terminal of the pull-up switching device even in the turn-off state of the pull-up switching device, i.e., even in the discharge state of the first node.
In other words, the pull-up switching device is turned-on once during one frame, and also the pull-up switching device outputs the clock pulse, which is inputted to the drain terminal thereof during the turned-on period, as the scan pulse. After that, as the pull-up switching device is turned-off until the next frame is started, the pull-up switching device can not output the clock pulse as the scan pulse even though the clock pulse is inputted to the drain terminal thereof during the turned-off period. According as the clock pulse is periodically applied to the drain terminal of the pull-up switching device, the coupling effect is generated between the first node connected with the gate terminal of the pull-up switching device and the drain terminal of the pull-up switching device. By the coupling effect, the first node is charged with the undesired voltage due to the clock pulse. That is, the first node is maintained in the charge state even at the undesired timing. In this case, the first node may be charged two or more times during one frame, whereby the pull-up switching device may be turned-on two or more times during one frame. Eventually, one stage may output scan pulses two or more times during one frame, thereby causing the multi-output.
A transistor for discharge is provided to prevent the coupling effect. The transistor for discharge responds to the signal outputted from the next stage, and discharges the first node of the corresponding stage, thereby preventing the first node from being charged. However, as the transistor for discharge is deteriorated, the pull-up transistor generates the multi-output due to the coupling effect. The deterioration of the transistor for discharge is caused by the connection between the dummy stage and the other stages, which will be explained in detail.
That is, the dummy stage of the shift register supplies the scan pulse to the n-th stage. However, the dummy stage doesn't supply the scan pulse to the gate line. In other words, the first to n-th stages are connected with the first to n-th gate lines. However, the dummy stage is not connected with the gate line. The gate line functions as one load. Accordingly, the scan pulse outputted from the dummy stage which is not connected with the gate line is larger in value than the scan pulse outputted from the other stages.
The scan pulse outputted from the dummy stage is supplied to the prior stage, and more particularly, to the transistor for discharge provided in the n-th stage. However, the value of the scan pulse outputted from the dummy stage is larger than the value of the scan pulse outputted from the next stage. Accordingly, the transistor for discharge of the n-th stage, to which the scan pulse is applied, can be easily deteriorated. In this case, it is difficult for the transistor to perform the discharge of the first node of the n-th stage. Accordingly, the n-th stage may generate the multi-output due to the coupling effect. The multi-output of the n-th stage is supplied to the prior stage, i.e., (n−1)-th stage. The multi-output is abnormal, whereby the transistor for discharge provided in the (n−1)-th stage is easily deteriorated.
As a result, the discharge transistors, provided in the stages, deteriorate, thereby generating the multi-output. That is, the picture quality of the LCD panel deteriorates due to one stage outputting scan pulses several times during one frame period.